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Publications

Architecture

 
 
__/__/2009
High-Level Reconfiguration Modelling

A. Raabe and A. Felke

Languages for Embedded Systems and Their Applications, M. Radetzki, ed., Springer
__/__/2009
The Manycore Revolution: Will HPC Lead or Follow?

J. Shalf, K. Asanović, D. Patterson, K. Keutzer, T. Mattson, and K. Yelick

SciDAC Review, No. 14, pp. 40-49, Fall 2009
10/__/2009
A View of the Parallel Computing Landscape

K. Asanovic, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. D. Kubiatowicz, N. Morgan, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick

Communications of the ACM, Vol. 52, No. 10, pp. 56-67
10/__/2009
Store Buffer Design for Multibanked Data Caches

E. Torres, P. Ibáñez, V. Viñals-Yúfera, and J. Maria Llaberia

IEEE Transactions on Computers, Vol. 58, No. 10, pp. 1307-1320
09/__/2009
SEJITS: Getting Productivity AND Performance With Selective Embedded JIT Specialization

B. Catanzaro, S. Kamil, Y. Lee, K. Asanovic, J. Demmel, K. Keutzer, J. Shalf, K. Yelick, and A. Fox

To appear in the proceedings of the First Workshop on Programmable Models for Emerging Architecture (PMEA) at the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT'09), Raleigh, North Carolina
07/__/2009
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popović, H. Li, H. Smith, J. Hoyt, F. Kärtner, R. Ram, V. Stojanović, and K. Asanović

IEEE Micro, Vol. 29, Issue 4, pp. 8-21
06/__/2009
Designing Multi-Socket Systems Using Silicon Photonics

S. Beamer, K. Asanović, C. Batten, A. Joshi, and V. Stojanović

Proceedings of the 23rd International Conference on Supercomputing (ICS-09), Yorktown Heights, New York, pp. 521-522
05/__/2009
Manycore Processor Networks with Monolithic Integrated CMOS Photonics

V. Stojanović, A. Joshi, C. Batten, Y.-J. Kwon, and K. Asanović

Proceedings of the 29th Conference on Lasers and Electro-Optics (CLEO'09) (invited paper), Baltimore, Maryland
05/__/2009
Silicon-Photonic Clos Networks for Global On-Chip Communication

A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanović, and V. Stojanović

To appear in the proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chips (NoCS 2009), San Diego, California
03/__/2009
Parallelizing the Web Browser

C. G. Jones, R. Liu, L. Meyerovich, K. Asanović, and R. Bodik

Proceedings of the First USENIX Workshop on Hot Topics in Parallelism (HotPar’09), Berkeley, California
03/__/2009
Tessellation: Space-Time Partitioning in a Manycore Client OS

R. Liu, K. Klues, S. Bird, S. Hofmeyr, K. Asanović, and J. Kubiatowicz

Proceedings of the First USENIX Workshop on Hot Topics in Parallelism (HotPar’09), Berkeley, California
03/__/2009
Lithe: Enabling Efficient Composition of Parallel Libraries

H. Pan, B. Hindman, and K. Asanović

Proceedings of the First USENIX Workshop on Hot Topics in Parallelism (HotPar’09), Berkeley, California
02/__/2009
An Exact and Efficient Triangle Intersection Test Hardware

A. Raabe, J. Tietjen, and J. K. Anlauf

Proceedings of the International Conference on Computer Graphics Theory and Applications (GRAPP ’09), Lisbon, Portugal, pp. 355-360
11/__/2008
The Case for Malleable Stream Architectures

C. Batten, H. Aoki, and K. Asanovic

Presented at the Workshop on Streaming Systems at IEEE/ACM International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy
09/__/2008
A SYSTEMC Language Extension for High-Level Reconfiguration Modeling

A. Raabe and A. Felke

Proceedings of Forum on Specification, Verification, and Design Lanaguages (FDL 08), Stuttgart, Germany, pp. 55-60
08/__/2008
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kärtner, R. Ram, V. Stojanovic, and K. Asanovic

Proceedings of IEEE Symposium on High-Performance Interconnects (Hot Interconnects 2008), Stanford, California, pp. 21-30
07/__/2008
Implementing the Scale Vector-Thread Processor

R. Krashinsky, C. Batten, and K. Asanović

ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 13, Issue 3, pp. 41:1-41:24
06/__/2008
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks

J.W. Lee, A. Ng, and K. Asanović

Proceedings of 35th International Symposium on Computer Architecture (ISCA), Beijing, China, pp. 89-100
06/__/2008
An FPGA Host-Multithreaded Functional Model for SPARC v8

Z. Tan, K. Asanovic and D. A. Patterson

Proceedings of the Workshop on Architectural Prototyping at the International Symposium on Computer Architecture, Beijing, China
04/__/2008
Compiling for Vector-Thread Architectures

M. Hampton and K. Asanovic

Proceedings of International Symposium on Code Generation and Optimization (CGO-2008), Boston, Massachusetts, pp. 205-215
03/__/2008
The Parallel Computing Laboratory at UC Berkeley: A Research Agenda Based on the Berkeley View

K. Asanovic, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. D. Kubiatowicz, E. A. Lee, N. Morgan, G. Necula, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick

UC Berkeley Electrical Engineering and Computer Sciences Department Technical Report UCB/EEECS-2008-23
11/__/2007
Transactors for Parallel Hardware and Software Co-design

K. Asanovic

Proceedings of the IEEE International High Level Design Validation and Test Workshop 2007 (HLDVT-2007) (invited paper), Irvine, California, pp. 140-142
10/__/2007
Continual Hashing for Efficient Fine-Grain State Inconsistency Checking

J.W. Lee, M. King, and K. Asanović

Proceedings of IEEE International Conference on Computer Design (ICCD-2007), Lake Tahoa, California, pp. 33-40
09/__/2007
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy

S. Heo, R. Krashinsky, and K. Asanovic

IEEE Transactions on VLSI Systems, Vol. 15, Issue 9, pp. 1060-1064
06/__/2007
The Scale Vector-Thread Processor

R. Krashinsky, C. Batten, and K. Asanović

Winner, DAC/ISSCC Student Design Contest, Design Automation Conference, DAC/ISSCC, San Diego, California
04/__/2007
RAMP: Research Accelerator for Multiple Processors

J. Wawrzynek, D. Patterson, M. Oskin, S.-L. Lu, C. Kozyrakis, J.C. Hoe, D. Chiou, and K. Asanovic

IEEE Micro, Vol. 27, Issue 2, pp. 46-57
01/__/2007
Scale Control Processor Test-chip

C. Batten, R. Krashinsky, and K. Asanović

Technical Report MIT-CSAIL-TR-2007-003, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology

 

 

    
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