Hierarchical Node Clustering in Polymorphic Processor Arrays
| Title | Hierarchical Node Clustering in Polymorphic Processor Arrays |
| Publication Type | Technical Report |
| Year of Publication | 1991 |
| Authors | Maresca, M., & Li H. |
| Other Numbers | 672 |
| Abstract | Massively parallel computers are implemented by means of modules at different packaging levels. This paper discusses a hierarchical node clustering scheme (HNC) for packaging a class of reconfigurable processor arrays called Polymorphic Processor Arrays (PPA) which use circuit-switching-based routers at each node to deliver a different topology at every instruction. The PPA family suffers from an unknown signal delay between two arbitrary nodes connected by the circuit- switched paths. This either forces the hardware clock to compromise to the worst signal or makes the software dependent on the system size. The use of the HNC scheme allows one to obtain communication speed-up and automatic control, at the compiler lever, over signal propagation delay. |
| URL | http://www.icsi.berkeley.edu/pubs/techreports/tr-91-042.pdf |
| Bibliographic Notes | ICSI Technical Report TR-91-042 |
| Abbreviated Authors | M. Maresca and Hungwen Li |
| ICSI Publication Type | Technical Report |