SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations

TitleSPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations
Publication TypeTechnical Report
Year of Publication1991
AuthorsAsanović, K., Beck J., Kingsbury B., Kohn P., Morgan N., & Wawrzynek J.
Other Numbers702

SPERT (Synthetic PERceptron Testbed) is a fully programmable single chip microprocessor designed for efficient execution of artificial neural network algorithms. The first implementation will be in a 1.2 micron CMOS technology with a 50MHz clock rate, and a prototype system is being designed to occupy a double SBus slot within a Sun Sparcstation.SPERT will sustain over 300 million connections per second during pattern classification, and around 100 million connection updates per second while running the popular error backpropagation training algorithm. This represents a speedup of around two orders of magnitude over a Sparcstation-2 for algorithms of interest. An earlier system produced by our group, the Ring Array Processor (RAP), used commercial DSP chips. Compared with a RAP multiprocessor of similar performance, SPERT represents over an order of magnitude reduction in cost for problems where fixed-point arithmetic is satisfactory.This report describes the current architecture, and gives the results of detailed simulations. The report also makes a short comparison to other high-performance digital neurocomputing chips.

Bibliographic Notes

ICSI Technical Report TR-91-072

Abbreviated Authors

K. Asanovic, J. Beck, B. E. D. Kingsbury, P. Kohn, N. Morgan, and J. Wawrzynek

ICSI Publication Type

Technical Report