Efficient VLSI Implementations of Vector-Thread Architectures

We present a taxonomy and modular implementation approach for data-parallel accelerators, includingthe MIMD, vector-SIMD, subword-SIMD, SIMT, and vector-thread (VT) architectural designpatterns. We introduce Maven, a new VT microarchitecture based on the traditional vector-SIMDmicroarchitecture, that is considerably simpler to implement and easier to program than previousVT designs. Using an extensive design-space exploration of full VLSI implementations of manyaccelerator design points, we evaluate the varying tradeoffs between programmability and implementationefficiency among the MIMD, vector-SIMD, and VT patterns on a workload of compiledmicrobenchmarks and application kernels. We find the vector cores provide greater efficiency thanthe MIMD cores, even on fairly irregular kernels. Our results suggest that the Maven VT microarchitectureis superior to the traditional vector-SIMD architecture, providing both greater efficiencyand easier programmability.

EECS Department, UC Berkeley Technical Report No. UCB/EECS-2011-129, Berkeley, California

Architecture