Publication Details
Title: HiPNeT-1: A Highly Pipelined Architecture for Neural Network Training
Author: K. Asanovic, B. E. D. Kingsbury, N. Morgan, and J. Wawrzynek
Group: ICSI Technical Reports
Date: June 1991
PDF: ftp://ftp.icsi.berkeley.edu/pub/techreports/1991/tr-91-035.pdf
Overview:
Current artificial neural network (ANN) algorithms require extensive computational resources. However, they exhibit massive fine-grained parallelism and require only moderate arithmetic precision. These properties make possible custom VLSI implementations for high performance, low cost systems. This paper describes one such system, a special purpose digital VLSI architecture to implement neural network training in a speech recognition application. The network algorithm has a number of atypical features. These include: shared weights, sparse activation, binary inputs, and a serial training input stream. The architecture illustrates a number of design techniques to exploit these algorithm-specific features. The result is a highly pipelined system which sustains a learning rate of one pattern per clock cycle. At a clock rate of 20MHz each "neuron" site performs 200 million connection updates per second. Multiple such neurons can be integrated onto a modestly sized VLSI die.
Bibliographic Information:
ICSI Technical Report TR-91-035
Bibliographic Reference:
K. Asanovic, B. E. D. Kingsbury, N. Morgan, and J. Wawrzynek. HiPNeT-1: A Highly Pipelined Architecture for Neural Network Training. ICSI Technical Report TR-91-035, June 1991
Author: K. Asanovic, B. E. D. Kingsbury, N. Morgan, and J. Wawrzynek
Group: ICSI Technical Reports
Date: June 1991
PDF: ftp://ftp.icsi.berkeley.edu/pub/techreports/1991/tr-91-035.pdf
Overview:
Current artificial neural network (ANN) algorithms require extensive computational resources. However, they exhibit massive fine-grained parallelism and require only moderate arithmetic precision. These properties make possible custom VLSI implementations for high performance, low cost systems. This paper describes one such system, a special purpose digital VLSI architecture to implement neural network training in a speech recognition application. The network algorithm has a number of atypical features. These include: shared weights, sparse activation, binary inputs, and a serial training input stream. The architecture illustrates a number of design techniques to exploit these algorithm-specific features. The result is a highly pipelined system which sustains a learning rate of one pattern per clock cycle. At a clock rate of 20MHz each "neuron" site performs 200 million connection updates per second. Multiple such neurons can be integrated onto a modestly sized VLSI die.
Bibliographic Information:
ICSI Technical Report TR-91-035
Bibliographic Reference:
K. Asanovic, B. E. D. Kingsbury, N. Morgan, and J. Wawrzynek. HiPNeT-1: A Highly Pipelined Architecture for Neural Network Training. ICSI Technical Report TR-91-035, June 1991