Publication Details
Title: Recent Work in VLSI Elements for Digital Implementations of Artificial Neural Networks
Author: B. E. D. Kingsbury, B. Irissou, K. Asanovic, J. Wawrzynek, and N. Morgan
Group: ICSI Technical Reports
Date: December 1991
PDF: ftp://ftp.icsi.berkeley.edu/pub/techreports/1991/tr-91-074.pdf
Overview:
A family of high-performance, area-efficient VLSI elements is being developed to simplify the design of artificial neural network processors. The libraries are designed around the MOSIS Scalable CMOS design rules, giving users the option of fabricating designs in 2.0um or 1.2um n-well processes, and greatly simplifying migration of the libraries to new MOSIS technologies. To date, libraries and generators have been created for saturating and nonsaturating adders, a two's-complement multiplier, and a triple-ported register file. The SPERT processor currently being designed at ICSI will be based upon these libraries, and is expected to run at 50 MHz when realized in a 1.2um CMOS technology.
Bibliographic Information:
ICSI Technical Report TR-91-074
Bibliographic Reference:
B. E. D. Kingsbury, B. Irissou, K. Asanovic, J. Wawrzynek, and N. Morgan. Recent Work in VLSI Elements for Digital Implementations of Artificial Neural Networks. ICSI Technical Report TR-91-074, December 1991
Author: B. E. D. Kingsbury, B. Irissou, K. Asanovic, J. Wawrzynek, and N. Morgan
Group: ICSI Technical Reports
Date: December 1991
PDF: ftp://ftp.icsi.berkeley.edu/pub/techreports/1991/tr-91-074.pdf
Overview:
A family of high-performance, area-efficient VLSI elements is being developed to simplify the design of artificial neural network processors. The libraries are designed around the MOSIS Scalable CMOS design rules, giving users the option of fabricating designs in 2.0um or 1.2um n-well processes, and greatly simplifying migration of the libraries to new MOSIS technologies. To date, libraries and generators have been created for saturating and nonsaturating adders, a two's-complement multiplier, and a triple-ported register file. The SPERT processor currently being designed at ICSI will be based upon these libraries, and is expected to run at 50 MHz when realized in a 1.2um CMOS technology.
Bibliographic Information:
ICSI Technical Report TR-91-074
Bibliographic Reference:
B. E. D. Kingsbury, B. Irissou, K. Asanovic, J. Wawrzynek, and N. Morgan. Recent Work in VLSI Elements for Digital Implementations of Artificial Neural Networks. ICSI Technical Report TR-91-074, December 1991