| Manycore Processor Networks with Monolithic Integrated CMOS Photonics | V. Stojanović, A. Joshi, C. Batten, Y.-J. Kwon, and K. Asanović | Proceedings of the 29th Conference on Lasers and Electro-Optics (CLEO'09) (invited paper), Baltimore, Maryland | May 2009 | Architecture | [PDF]
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| Silicon-Photonic Clos Networks for Global On-Chip Communication | A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanović, and V. Stojanović | Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chips (NoCS 2009), San Diego, California, pp. 124-133 | May 2009 | Architecture | [PDF]
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| Designing Multi-Socket Systems Using Silicon Photonics | S. Beamer, K. Asanović, C. Batten, A. Joshi, and V. Stojanović | Proceedings of the 23rd International Conference on Supercomputing (ICS-09), Yorktown Heights, New York, pp. 521-522 | June 2009 | Architecture | [PDF]
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| Store Buffer Design for Multibanked Data Caches | E. Torres, P. Ibáñez, V. Viñals-Yúfera, and J. Maria Llaberia | IEEE Transactions on Computers, Vol. 58, No. 10, pp. 1307-1320 | October 2009 | Architecture | [PDF]
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| Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics | C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popović, H. Li, H. Smith, J. Hoyt, F. Kärtner, R. Ram, V. Stojanović, and K. Asanović | IEEE Micro, Vol. 29, Issue 4, pp. 8-21 | July 2009 | Architecture | [PDF]
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| SEJITS: Getting Poductivity AND Performance with Selective Embedded JIT Specialization | B. Catanzaro, S. Kamil, Y. Lee, K. Asanovic, J. Demmel, K. Keutzer, J. Shalf, K. Yelick, and A. Fox | Presented at the First Workshop on Programmable Models for Emerging Architecture (PMEA) at the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT'09), Raleigh, North Carolina | September 2009 | Architecture | [PDF]
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| The Manycore Revolution: Will HPC Lead or Follow? | J. Shalf, K. Asanović, D. Patterson, K. Keutzer, T. Mattson, and K. Yelick | SciDAC Review, No. 14, pp. 40-49, Fall 2009 | 2009 | Architecture | [PDF]
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| A Design-Space Exploration for CMOS Photonic Processor Networks | V. Stojanović, A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, S. Chen, and K. Asanović | Invited talk at the Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC 2010), San Diego, California | March 2010 | Architecture | |
| Composing Parallel Software Efficiently with Lithe | H. Pan, B. Hindman, and K. Asanović | Proceedings of the Programming Language Design and Implementation (PLDI 2010), Toronto, Canada, pp. 376-387 | June 2010 | Architecture | |
| An FPGA-Based Simulator for Datacenter Networks | Z. Tan, K. Asanovic, and D. Patterson | Presented at the Exascale Evaluation and Research Techniques Workshop, Pittsburgh, Pennsylvania | March 2010 | Architecture | |
| Guest Editors' Introduction: Proceedings of the 21st Symposium on High Performance Chips (Hot Chips 21), Stanford, California | K. Asanovic and R. Wittig | IEEE Micro, Vol. 30, No. 2, pp. 5-6 | March 2010 | Architecture | [PDF]
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| A Case for FAME: FPGA Architecture Model Execution | Z. Tan, A. Waterman, H. Cook, S. Bird, K. Asanović, and D. Patterson | Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), Saint-Malo, France, pp. 290-301 | June 2010 | Architecture | [PDF]
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| Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics | S. Beamer, C. Sun, Y.-J. Kwon, A. Joshi, C. Batten, V. Stojanović, and K. Asanović | Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), Saint-Malo, France, pp. 129-140 | June 2010 | Architecture | [PDF]
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| Resource Management in the Tessellation Manycore OS | J. A. Colmenares, S. Bird, H. Cook, P. Pearce, D. Zhu, J. Shalf, K. Asanović, and J. Kubiatowicz | Proceedings of the Second USENIX Workshop on Hot Topics in Parallelism (HotPar'10), Berkeley, California | June 2010 | Architecture | [PDF]
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| RAMP Gold: An FPGA-Based Architecture Simulator for Multiprocessors | Z. Tan, A. Waterman, R. Avizienis, Y. Lee, H. Cook, D. Patterson, and K. Asanović | Proceedings of the 47th Design Automation Conference (DAC 2010), Anaheim, California | June 2010 | Architecture | [PDF]
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| Low-Cost Tuning of Two-Step Algorithms for Scheduling Mixed-Parallel Applications onto Homogeneous Clusters | S. Hunold | Proceedings of the 10th IEEE/ACM International Symposium on Cluster, Cloud, and Grid Computing (CCGrid 2010), Melbourne, Australia, pp. 253-261 | May 2010 | Architecture | [PDF]
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| Jedule: A Tool for Visualizing Schedules of Parallel Applications | S. Hunold, R. Hoffmann, and F. Suter | Proceedings of the 39th International Conference on Parallel Processing Workshops (ICPPW 2010), San Diego, California, pp. 169-178 | September 2010 | Architecture | [PDF]
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| BPEL Remote Objects: Integrating BPEL Processes into Object-Oriented Applications | M. Ferber, S. Hunold, and T. Rauber | Proceedings of the 7th International Conference on Services Computing (IEEE SCC 2010), Miami, Florida | July 2010 | Architecture | [PDF]
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| Combining Object-Oriented Design and SOA with Remote Objects over Web Services | M. Ferber, T. Rauber, and S. Hunold | Proceedings of the 8th IEEE European Conference on Web Services, Ayia Napa, Cyprus, pp. 83-90 | December 2010 | Architecture | [PDF]
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| Datacenter-Scale Network Research on FPGAs | Z. Tan, K. Asanovic, and D. Patterson | Proceedings of the Exascale Evaluation and Research Techniques Workshop (EXERT 2011) at the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2011), Newport Beach, California | March 2011 | Architecture | [PDF]
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| Exploring the Tradeoffs Between Programmability and Efficiency in Data-Parallel Accelerators | Y. Lee, R. Avizienis, A. Bishara, R. Xia, D. Lockhart, C. Batten, and K. Asanovic | Proceedings of the International Symposium on Computer Architecture (ISCA-2011), pp. 129-140, San Jose, California | June 2011 | Architecture | [PDF]
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| The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA | A. Waterman, Y. Lee, D. Patterson, and K. Asanovic | EECS Department, UC Berkeley Technical Report No. UCB/EECS-2011-62, Berkeley, California | May 2011 | Architecture | [PDF]
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| Efficient VLSI Implementations of Vector-Thread Architectures | Y. Lee | UC Berkeley Master's thesis, Berkeley, California. Also EECS Department, UC Berkeley Technical Report No. UCB/EECS-2011-129, Berkeley, California | December 2011 | Architecture | [PDF]
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| Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed | A. S. Waterman | UC Berkeley Master's thesis, Berkeley, California. Also EECS Department, UC Berkeley Technical Report No. UCB/EECS-2011-63, Berkeley, California | May 2011 | Architecture | [PDF]
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| CPU Accounting for Multicore Processors | C. Luque, M. Moretó, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero | IEEE Transactions on Computers. Vol. 61, Issue 2 | February 2012 | Architecture | |
| Optimal Task Assignment in Multithreaded Processors: A Statistical Approach | P. Radojkovic, V. Cakarevic, M. Moretó, J. Verdu, A. Pajuelo, F. J. Cazorla, M. Nemirovsky, and M. Valero | Architectural Support for Programming Languages and Operating Systems (ASPLOS). London, United Kingdom | March 2012 | Architecture | |
| Direction-Optimizing Breadth-First Search | S. Beamer, K. Asanović, and D. Patterson | Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC12), Article No. 12, Salt Lake City, Utah | November 2012 | Architecture | |
| ICSI Gazette | | | March 2011 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | March 2007 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | September 2006 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | March 2006 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | September 2005 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | March 2005 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | September 2004 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | March 2004 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | September 2003 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | September 2007 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | March 2008 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | September 2008 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | March 2009 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | September 2009 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | March 2010 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | September 2010 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | September 2011 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | May 2012 | ICSI Newsletter | [PDF]
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| ICSI Gazette | | | September 2012 | ICSI Newsletter | [PDF]
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| Auditory model for parametrization of speech | H. Hermansky, N. Morgan, and P. Kohn | United States Patent 5,450,522. U.S. Class 704/200.1, 704/205. International Class G10L 009/00. Field of Search 381/29-53 395/2.1-2.39 | September 12 1995 | Patents | |
| Noise resistant auditory model for parametrization of speech | H. Hermansky and N. Morgan | United States Patent 5,537,647. U.S. Class 704/211, 704/200.1, 704/201, 704/217, 704/219, 704/226. International Class G01L 003/02, G01L 009/00. Field of Search 381/46-47 395/2.35,2.36,2.37,2.42,2,2.2,2.1,2.39 | July 16 1996 | Patents | |
| Vector processing system with multi-operation, run-time configurable pipelines | K. Asanovic | United States Patent 5,805,875. U.S. Class 712/222, 712/200. International Class G06F 9/318 (20060101), G06F 15/76 (20060101), G06F 15/78 (20060101), G06F 9/38 (20060101). Field of Search 395/376,563 | September 08 1998 | Patents | |
| System for packetizing data encoded corresponding to priority levels where reconstructed data corresponds to fractionalized priority level and received franctionalized packets | A. Albanese, M. Luby, J. Bloemer, and J. Edmonds | United States Patent 5,617,541. U.S. Class 709/207, 380/42, 707/100, 709/233, 714/5, 714/755. International Class G06F 003/00. Field of Search 341/50 364/240.8,241,960.61,960.62,941.6,943.9 371/30,48,37.4 395/200.06,700,600,182.03,200.13 380/42 | March 26 2007 | Patents | |
