| Scale Control Processor Test-chip | C. Batten, R. Krashinsky, and K. Asanović | Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology Technical Report No. MIT-CSAIL-TR-2007-003, Cambridge, Massachusetts | January 2007 | Architecture | [PDF]
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| The Scale Vector-Thread Processor | R. Krashinsky, C. Batten, and K. Asanović | Winner, DAC/ISSCC Student Design Contest, Design Automation Conference, DAC/ISSCC, San Diego, California | June 2007 | Architecture | |
| Continual Hashing for Efficient Fine-Grain State Inconsistency Checking | J.W. Lee, M. King, and K. Asanović | Proceedings of IEEE International Conference on Computer Design (ICCD-2007), Lake Tahoe, California, pp. 33-40 | October 2007 | Architecture | [PDF]
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| Transactors for Parallel Hardware and Software Co-design | K. Asanovic | Proceedings of the IEEE International High Level Design Validation and Test Workshop 2007 (HLDVT-2007) (invited paper), Irvine, California, pp. 140-142 | November 2007 | Architecture | [PDF]
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| Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics | C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kärtner, R. Ram, V. Stojanovic, and K. Asanović | Proceedings of IEEE Symposium on High-Performance Interconnects (Hot Interconnects 2008), Stanford, California, pp. 21-30 | August 2008 | Architecture | [PDF]
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| Implementing the Scale Vector-Thread Processor | R. Krashinsky, C. Batten, and K. Asanović | ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 13, Issue 3, pp. 41:1-41:24 | July 2008 | Architecture | [PDF]
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| An FPGA Host-Multithreaded Functional Model for SPARC v8 | Z. Tan, K. Asanović and D. A. Patterson | Proceedings of the Workshop on Architectural Prototyping at the International Symposium on Computer Architecture, Beijing, China | June 2008 | Architecture | [PDF]
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| Compiling for Vector-Thread Architectures | M. Hampton and K. Asanović | Proceedings of International Symposium on Code Generation and Optimization (CGO-2008), Boston, Massachusetts, pp. 205-215 | April 2008 | Architecture | [PDF]
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| The Parallel Computing Laboratory at UC Berkeley: A Research Agenda Based on the Berkeley View | K. Asanovic, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. D. Kubiatowicz, E. A. Lee, N. Morgan, G. Necula, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick | EECS Department, UC Berkeley Technical Report No. UCB/EEECS-2008-23, Berkeley, California | March 2008 | Architecture | [PDF]
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| The Case for Malleable Stream Architectures | C. Batten, H. Aoki, and K. Asanović | Presented at the Workshop on Streaming Systems at IEEE/ACM International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy | November 2008 | Architecture | |
| An Exact and Efficient Triangle Intersection Test Hardware | A. Raabe, J. Tietjen, and J. K. Anlauf | Proceedings of the International Conference on Computer Graphics Theory and Applications (GRAPP ’09), Lisbon, Portugal, pp. 355-360 | February 2009 | Architecture | [PDF]
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| High-Level Reconfiguration Modelling | A. Raabe and A. Felke | Languages for Embedded Systems and Their Applications, M. Radetzki, ed., pp. 227-240, Springer | 2009 | Architecture | |
| A SYSTEMC Language Extension for High-Level Reconfiguration Modeling | A. Raabe and A. Felke | Proceedings of Forum on Specification, Verification, and Design Languages (FDL 08), Stuttgart, Germany, pp. 55-60 | September 2008 | Architecture | [PDF]
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| A View of the Parallel Computing Landscape | K. Asanović, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. D. Kubiatowicz, N. Morgan, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick | Communications of the ACM, Vol. 52, No. 10, pp. 56-67 | October 2009 | Architecture | [PDF]
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| Parallelizing the Web Browser | C. G. Jones, R. Liu, L. Meyerovich, K. Asanović, and R. Bodik | Proceedings of the First USENIX Workshop on Hot Topics in Parallelism (HotPar’09), Berkeley, California | March 2009 | Architecture | [PDF]
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| Tessellation: Space-Time Partitioning in a Manycore Client OS | R. Liu, K. Klues, S. Bird, S. Hofmeyr, K. Asanović, and J. Kubiatowicz | Proceedings of the First USENIX Workshop on Hot Topics in Parallelism (HotPar’09), Berkeley, California | March 2009 | Architecture | [PDF]
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| Lithe: Enabling Efficient Composition of Parallel Libraries | H. Pan, B. Hindman, and K. Asanović | Proceedings of the First USENIX Workshop on Hot Topics in Parallelism (HotPar’09), Berkeley, California | March 2009 | Architecture | [PDF]
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| Manycore Processor Networks with Monolithic Integrated CMOS Photonics | V. Stojanović, A. Joshi, C. Batten, Y.-J. Kwon, and K. Asanović | Proceedings of the 29th Conference on Lasers and Electro-Optics (CLEO'09) (invited paper), Baltimore, Maryland | May 2009 | Architecture | [PDF]
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| Silicon-Photonic Clos Networks for Global On-Chip Communication | A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanović, and V. Stojanović | Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chips (NoCS 2009), San Diego, California, pp. 124-133 | May 2009 | Architecture | [PDF]
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| Designing Multi-Socket Systems Using Silicon Photonics | S. Beamer, K. Asanović, C. Batten, A. Joshi, and V. Stojanović | Proceedings of the 23rd International Conference on Supercomputing (ICS-09), Yorktown Heights, New York, pp. 521-522 | June 2009 | Architecture | [PDF]
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| Store Buffer Design for Multibanked Data Caches | E. Torres, P. Ibáñez, V. Viñals-Yúfera, and J. Maria Llaberia | IEEE Transactions on Computers, Vol. 58, No. 10, pp. 1307-1320 | October 2009 | Architecture | [PDF]
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| Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics | C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popović, H. Li, H. Smith, J. Hoyt, F. Kärtner, R. Ram, V. Stojanović, and K. Asanović | IEEE Micro, Vol. 29, Issue 4, pp. 8-21 | July 2009 | Architecture | [PDF]
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| SEJITS: Getting Poductivity AND Performance with Selective Embedded JIT Specialization | B. Catanzaro, S. Kamil, Y. Lee, K. Asanovic, J. Demmel, K. Keutzer, J. Shalf, K. Yelick, and A. Fox | Presented at the First Workshop on Programmable Models for Emerging Architecture (PMEA) at the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT'09), Raleigh, North Carolina | September 2009 | Architecture | [PDF]
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| The Manycore Revolution: Will HPC Lead or Follow? | J. Shalf, K. Asanović, D. Patterson, K. Keutzer, T. Mattson, and K. Yelick | SciDAC Review, No. 14, pp. 40-49, Fall 2009 | 2009 | Architecture | [PDF]
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| A Design-Space Exploration for CMOS Photonic Processor Networks | V. Stojanović, A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, S. Chen, and K. Asanović | Invited talk at the Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC 2010), San Diego, California | March 2010 | Architecture | |
| Composing Parallel Software Efficiently with Lithe | H. Pan, B. Hindman, and K. Asanović | Proceedings of the Programming Language Design and Implementation (PLDI 2010), Toronto, Canada, pp. 376-387 | June 2010 | Architecture | |
| An FPGA-Based Simulator for Datacenter Networks | Z. Tan, K. Asanovic, and D. Patterson | Presented at the Exascale Evaluation and Research Techniques Workshop, Pittsburgh, Pennsylvania | March 2010 | Architecture | |
| Guest Editors' Introduction: Proceedings of the 21st Symposium on High Performance Chips (Hot Chips 21), Stanford, California | K. Asanovic and R. Wittig | IEEE Micro, Vol. 30, No. 2, pp. 5-6 | March 2010 | Architecture | [PDF]
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| A Case for FAME: FPGA Architecture Model Execution | Z. Tan, A. Waterman, H. Cook, S. Bird, K. Asanović, and D. Patterson | Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), Saint-Malo, France, pp. 290-301 | June 2010 | Architecture | [PDF]
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| Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics | S. Beamer, C. Sun, Y.-J. Kwon, A. Joshi, C. Batten, V. Stojanović, and K. Asanović | Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), Saint-Malo, France, pp. 129-140 | June 2010 | Architecture | [PDF]
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| Resource Management in the Tessellation Manycore OS | J. A. Colmenares, S. Bird, H. Cook, P. Pearce, D. Zhu, J. Shalf, K. Asanović, and J. Kubiatowicz | Proceedings of the Second USENIX Workshop on Hot Topics in Parallelism (HotPar'10), Berkeley, California | June 2010 | Architecture | [PDF]
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| RAMP Gold: An FPGA-Based Architecture Simulator for Multiprocessors | Z. Tan, A. Waterman, R. Avizienis, Y. Lee, H. Cook, D. Patterson, and K. Asanović | Proceedings of the 47th Design Automation Conference (DAC 2010), Anaheim, California | June 2010 | Architecture | [PDF]
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| Low-Cost Tuning of Two-Step Algorithms for Scheduling Mixed-Parallel Applications onto Homogeneous Clusters | S. Hunold | Proceedings of the 10th IEEE/ACM International Symposium on Cluster, Cloud, and Grid Computing (CCGrid 2010), Melbourne, Australia, pp. 253-261 | May 2010 | Architecture | [PDF]
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| Jedule: A Tool for Visualizing Schedules of Parallel Applications | S. Hunold, R. Hoffmann, and F. Suter | Proceedings of the 39th International Conference on Parallel Processing Workshops (ICPPW 2010), San Diego, California, pp. 169-178 | September 2010 | Architecture | [PDF]
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| BPEL Remote Objects: Integrating BPEL Processes into Object-Oriented Applications | M. Ferber, S. Hunold, and T. Rauber | Proceedings of the 7th International Conference on Services Computing (IEEE SCC 2010), Miami, Florida | July 2010 | Architecture | [PDF]
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| Combining Object-Oriented Design and SOA with Remote Objects over Web Services | M. Ferber, T. Rauber, and S. Hunold | Proceedings of the 8th IEEE European Conference on Web Services, Ayia Napa, Cyprus, pp. 83-90 | December 2010 | Architecture | [PDF]
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| Datacenter-Scale Network Research on FPGAs | Z. Tan, K. Asanovic, and D. Patterson | Proceedings of the Exascale Evaluation and Research Techniques Workshop (EXERT 2011) at the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2011), Newport Beach, California | March 2011 | Architecture | [PDF]
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| Exploring the Tradeoffs Between Programmability and Efficiency in Data-Parallel Accelerators | Y. Lee, R. Avizienis, A. Bishara, R. Xia, D. Lockhart, C. Batten, and K. Asanovic | Proceedings of the International Symposium on Computer Architecture (ISCA-2011), pp. 129-140, San Jose, California | June 2011 | Architecture | [PDF]
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| The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA | A. Waterman, Y. Lee, D. Patterson, and K. Asanovic | EECS Department, UC Berkeley Technical Report No. UCB/EECS-2011-62, Berkeley, California | May 2011 | Architecture | [PDF]
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| Efficient VLSI Implementations of Vector-Thread Architectures | Y. Lee | UC Berkeley Master's thesis, Berkeley, California. Also EECS Department, UC Berkeley Technical Report No. UCB/EECS-2011-129, Berkeley, California | December 2011 | Architecture | [PDF]
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| Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed | A. S. Waterman | UC Berkeley Master's thesis, Berkeley, California. Also EECS Department, UC Berkeley Technical Report No. UCB/EECS-2011-63, Berkeley, California | May 2011 | Architecture | [PDF]
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| CPU Accounting for Multicore Processors | C. Luque, M. Moretó, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero | IEEE Transactions on Computers. Vol. 61, Issue 2 | February 2012 | Architecture | |
| Optimal Task Assignment in Multithreaded Processors: A Statistical Approach | P. Radojkovic, V. Cakarevic, M. Moretó, J. Verdu, A. Pajuelo, F. J. Cazorla, M. Nemirovsky, and M. Valero | Architectural Support for Programming Languages and Operating Systems (ASPLOS). London, United Kingdom | March 2012 | Architecture | |
| Direction-Optimizing Breadth-First Search | S. Beamer, K. Asanović, and D. Patterson | Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC12), Article No. 12, Salt Lake City, Utah | November 2012 | Architecture | |
| Factorized Latent Spaces with Structured Sparsity | Y. Jia, M. Salzmann, and T. Darrell | Proceedings of the 24th Annual Conference on Neural Information Processing Systems (NIPS 2010), Vancouver, Canada, pp. 982-990 | December 2010 | Vision | [PDF]
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| Unsupervised Learning of Visual Sense Models for Polysemous Words | K. Saenko and T. Darrell | Proceedings of the 22nd Annual Conference on Neural Information Processing Systems (NIPS), Vancouver, Canada, pp. 1393-1400 | December 2008 | Vision | [PDF]
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| Multistream Articulatory Feature-Based Models for Visual Speech Recognition | K. Saenko, K. Livescu, J. Glass, and T. Darrell | IEEE Transactions on Pattern Analysis and Machine Intelligence (PAMI), Vol. 31, No. 9 | September 2009 | Vision | [PDF]
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| Photo-Based Question Answering | T. Yeh, J. Lee, and T. Darrell | Proceedings of 16th ACM International Conference on Multimedia 2008 (ACM Multimedia), Vancouver, Canada, pp. 389-398 | October 2008 | Vision | [PDF]
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| Local Probabilistic Regression for Activity-Independent Human Pose Inference | R. Urtasun and T. Darrell | Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR), Anchorage, Alaska | June 2008 | Vision | [PDF]
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| Topologically-Constrained Latent Variable Models | R. Urtasun, D. J. Fleet, A. Geiger, J. Popovic, T. Darrell, and N. D. Lawrence | Proceedings of International Conference on Machine Learning (ICML), Helsinki, Finland, pp. 1080-1087 | July 2008 | Vision | [PDF]
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