A Hybrid Fault Simulator for Synchronous Sequential Circuits

TitleA Hybrid Fault Simulator for Synchronous Sequential Circuits
Publication TypeTechnical Report
Year of Publication1994
AuthorsKrieger, R., Becker B., & Keim M.
Other Numbers878

Fault simulation for synchronous sequential circuits is a very time consuming task. The complexity of the task increases if there is no information about the initial state of the circuit available. In this case, an unknown initial state is assumed which is usually handled by introducing a three-valued logic. It is known, that fault simulation based upon this logic only determines a lower bound for the fault coverage achievable by a test sequence. Therefore, we developed a hybrid fault simulator H-FS combining the advantages of a fault simulator using the three-valued logic and of an exact symbolic fault simulator based upon binary decision diagrams. H-FS is able to handle even the largest benchmark circuits and thereby determines fault coverages much more accurately.

Bibliographic Notes

ICSI Technical Report TR-94-008

Abbreviated Authors

R. Krieger, B. Becker, and M. Keim

ICSI Publication Type

Technical Report