Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed

TitleImproving Energy Efficiency and Reducing Code Size with RISC-V Compressed
Publication TypeThesis
Year of Publication2011
AuthorsWaterman, A.
Other Numbers3245
Abstract

Delivering the instruction stream can be the largest source of energy consumption in aprocessor, yet loosely-encoded RISC instruction sets are wasteful of instruction bandwidth.Aiming to improve the performance and energy efficiency of the RISC-V ISA, this thesisproposes RISC-V Compressed (RVC), a variable-length instruction set extension. RVC is asuperset of the RISC-V ISA, encoding the most frequent instructions in half the size of a RISCVinstruction; the remaining functionality is still accessible with full-length instructions. RVC

URLhttp://www.icsi.berkeley.edu/pubs/arch/EECS-2011-63.pdf
Bibliographic Notes

UC Berkeley Master's thesis, Berkeley, California.

Abbreviated Authors

A. S. Waterman

ICSI Research Group

Architecture

ICSI Publication Type

Masters thesis