Designing Chip-Level Nanophotonic Interconnection Networks

TitleDesigning Chip-Level Nanophotonic Interconnection Networks
Publication TypeJournal Article
Year of Publication2012
AuthorsBatten, C., Joshi A., Stojanovic V., & Asanović K.
Published inIEEE Journal on Emerging and Selected Topics in Circuits and Systems
Other Numbers3894

Technology scaling will soon enable high-performanceprocessors with hundreds of cores integrated onto a singledie, but the success of such systems could be limited by thecorresponding chip-level interconnection networks. There havebeen many recent proposals for nanophotonic interconnectionnetworks that attempt to provide improved performance andenergy-efficiency compared to electrical networks. This paperdiscusses the approach we have used when designing such networks,and provides a foundation for designing new networks.We begin by briefly reviewing the basic silicon-photonic devicetechnology before outlining design issues and surveying previousnanophotonic network proposals at the architectural level, themicroarchitectural level, and the physical level. In designing ourown networks, we use an iterative process that moves betweenthese three levels of design to meet application requirementsgiven our technology constraints. We use our ongoing work onleveraging nanophotonics in an on-chip title-to-tile network,processor-to-main-memory network, and dynamic random-accessmemory (DRAM) channel to illustrate this design process.Index Terms—Interconnection networks, multicore/manycoreprocessors, nanophotonics, optical interconnect.

Bibliographic Notes

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, Issue 2, pp. 137-153, June 2012.

Abbreviated Authors

C. Batten, A. Joshi, V. Stojanovi?, and K. Asanovi?

ICSI Research Group


ICSI Publication Type

Article in journal or magazine